The present invention relates generally to the field of integrated circuits, and more particularly to testing integrated circuits.
Scan chains are chains of single-bit registers (e.g., flip-flops or latches) that can be used as data inputs and outputs for functional units in order to facilitate testing of the functional units. Scan chains are typically loaded with test data and unloaded with results data via a serial interface. For example, Wikipedia describes the following sequence for scan chains: 1) assert scan mode and set up the desired inputs, 2) de-assert scan mode and apply one clock to capture results in the target flip-flops, 3) re-assert scan mode, and see if the combinatorial test passed.